Semiconductor devices and methods of manufacturing thereof

ABSTRACT

A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of U.S. Provisional Application No. 63/211,630, filed Jun. 17, 2021, entitled “Cladding SiGe Smiling Improve for Multiple Layer Wet Etch,” which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a perspective view of a nanostructure transistor device, in accordance with some embodiments.

FIGS. 2A-B illustrates a flow chart of an example method for making a non-planar transistor device, in accordance with some embodiments.

FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11A, 12, 13, 14, 15, 16, 17A, and 18A illustrate perspective views of an example nanostructure transistor device (or a portion of the example nanostructure transistor device) during various fabrication stages, made by the method of FIGS. 2A-B, in accordance with some embodiments.

FIGS. 11B, 17B, and 18B illustrate cross-sectional views of the example nanostructure transistor device corresponding to FIGS. 11A, 17A, and 18A, respectively, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as field effect transistors are fabricated on a single wafer. Non-planar transistor device architectures, such as fin-based transistors (typically referred to as “FinFETs”), can provide increased device density and increased performance over planar transistors. Some advanced non-planar transistor device architectures such as nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, gate-all-around transistors, multi-bridge-channel transistors, nanoribbon transistors, etc.) can obtain great performance. The nanostructure transistor, in general, includes a gate structure that wraps around the perimeter of one or more nanostructures for improved control of channel current flow. For example, in a FinFET and a nanostructure transistor with similar dimensions, the nanostructure transistor can present larger driving current (I_(on)), smaller subthreshold leakage current (I_(off)), etc.

The present disclosure provides various embodiments of a method for fabricating a non-planar transistor device, which includes a sequential combination of at least a first etching process and a second etching process to pattern the cladding layer. The patterned cladding layer may have a vertical difference of less than 3 nanometers between a highest point of a top surface of the cladding layer and a lowest point of the top surface of the cladding layer. For example, a hard mask containing SiGe with a first percentage of germanium may be deposited on a plurality of semiconductor channel layers and a plurality of semiconductor sacrificial layers to form a fin structure. Next, the cladding layer also containing SiGe with a second percentage of germanium may be formed over the fin structure. The first percentage of the hard mask may be larger than the second percentage of the cladding layer. Then, the first etching process may include a wet etchant containing hydrofluoric acid and liquid ozone and may be applied over the hard mask and the cladding layer. The second etching process may include a wet etchant containing ammonium and hydrogen peroxide and may also be applied over the hard mask and the cladding layer.

The differences in the amount of germanium in the hard mask and the cladding layer as well as the two etching processes remove the hard mask and a portion of the cladding layer, resulting in vertical difference between the highest point and the lowest point of the top surface the cladding layer to be less than 3 nanometers. Such a relatively small vertical difference of the cladding layer (e.g., a relatively flat top surface when stated in another way) can provide various advantages during the whole fabrication process. For example, during a later stage of the fabrication process, the cladding layer may be removed. With such a relatively flat top surface, a processing window for at least the removal process of the cladding layer can be advantageously enhanced, which can in turn lower cost/time of the overall fabrication process.

FIG. 1 illustrates a perspective view of a non-planar transistor device 100, in accordance with various embodiments. In accordance with some embodiments, the non-planar device 100 includes a nanostructure transistor device. However, it should be understood that the device 100 can include any of various other types of transistor configurations, while remaining within the scope of present disclosure.

The nanostructure transistor device 100 includes a substrate 102 and a number of semiconductor layers 104 that may contain nanostructures (e.g., nanosheets, nanowires, etc.) above the substrate 102. The semiconductor layers 104 (which may sometimes be collectively referred to as a channel structure) are vertically separated from one another. Isolation structure 106 are formed on opposing ends of a protruded portion of the substrate 102 with the semiconductor layers 104 disposed above the protruded portion. A gate structure 108 wraps around each of the semiconductor layers 104 (e.g., a full perimeter of each of the semiconductor layers 104). Epitaxial structures 110 which may include source and drain regions are disposed on opposing sides of the gate structure 108. An interlayer dielectric (ILD) 112 is disposed over the epitaxial structure 110 and in between the epitaxial structure 110 and the isolation structure 106. FIG. 1 depicts a simplified nanostructure transistor device, and thus, it should be understood that one or more features of a completed nanostructure transistor device may not be shown in FIG. 1 . For example, the other epitaxial structure opposite the gate structure 108 from the epitaxial structure 110 and the ILD disposed over such an epitaxial structure are not shown in FIG. 1 .

FIG. 2 illustrates a flowchart a method 200 to form a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method 200 can be used to form a nanostructure transistor device such as, for example, a nanostructure transistor device, a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, or the like. Further, the method 200 can be used to form a nanostructure transistor device in a respective conduction type such as, for example an n-type nanostructure transistor device or a p-type nanostructure transistor device. The term “n-type,” as used herein, may be referred to as the conduction type of a transistor having electrons as its conduction carriers; and the term “p-type,” as used herein, may be referred to as the conduction type of a transistor having holes as its conduction carriers.

It is noted that the method 200 is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method 200 of FIG. 2 , and that some other operations may only be briefly described herein. In various embodiments, operations of the method 200 may be associated with perspective views of an example nanostructure transistor device at various fabrication stages as shown in FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11A, 12, 13, 14, 15, 16, 17A, and 18A. For purposes of clarity of illustration, FIGS. 11B, 17B, and 18B illustrate cross-sectional views of the example GAA transistor device corresponding to FIGS. 11A, 17A, and 18A, respectively.

In a brief overview, the method 200 starts at operation 202 of providing a substrate overlaid by a number of first semiconductor layers and a number of second semiconductor layer. The method 200 continues to operation 204 in which a hard mask and fin structures (or a fin structure with a stacked nanostructure) are formed. The method 200 continues to operation 206 in which isolation structures are formed. The method continues to operation 208 in which a cladding layer is formed. The method 200 continues to operation 210 in which a nitride-based dielectric layer is formed. The method 200 continues to operation 212 in which an oxide-based layer is formed. The method 200 continues to operation 214 in which an upper portion of the oxide-based layer. The method 200 continues to operation 216 in which the nitride-based dielectric layer is etched. The method 200 continues to operation 218 in which a high-k dielectric structure is formed. The method 200 continues to operation 220 in which the cladding layer is etched with the first etching process. The method 200 continues to operation 222 in which the cladding layer is etched with the 2 ^(nd) etching process.

The method 200 continues to operation 224 in which dummy gate structures are formed. The method 200 continues to operation 226 in which end portions of the first semiconductor layers are removed. The method 200 continues to operation 228 in which inner spacers are formed. The method 200 continues to operation 230 in which epitaxial structures are formed. The method 200 continues to operation 232 in which an ILD formed. The method 200 continues to operation 234 in which active gate structures are formed. The method 200 continues to operation 236 in which gate cut structures are formed.

As mentioned before, FIGS. 3-18B each illustrate, in either a cross-sectional or perspective view, a portion of a nanostructure transistor device 300, either in n-type or p-type, at various fabrication stages of the method 200 of FIG. 2 . For example, FIGS. 3-11A, 12-17A, and 18A illustrate perspective views of the nanostructure transistor device 300. FIGS. 11B, 17B, and 18B illustrate cross-sectional views of the nanostructure transistor device 300 along the X-direction which corresponds to a cross-section cut along the longitudinal direction of a gate trench or an active gate structure. FIGS. 11B, 17B, and 18B correspond to FIGS. 11A, 17A, and 18A, respectively. Although FIGS. 3-18B illustrate the nanostructure transistor device 300, it is understood the nanostructure transistor device 300 may include a number of other devices such as inductors, fuses, capacitors, coils, etc., which are not shown in FIGS. 3-18B for purposes of clarity of illustration.

Corresponding to operation 202 of FIG. 2 , FIG. 3 is a perspective view of a nanostructure transistor device 300 including a number of first semiconductor layers 304 and a number of second semiconductor layers 306 formed on a semiconductor substrate 302 at one of the various stages of fabrication. As shown in the illustrated example of FIG. 3 , the semiconductor layers 304 and 306 are formed as a stack over the semiconductor substrate 302.

The semiconductor substrate 302 includes a semiconductor material substrate, for example, silicon. Alternatively, the semiconductor substrate 302 may include other elementary semiconductor material such as, for example, germanium. The semiconductor substrate 302 may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. The semiconductor substrate 302 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the semiconductor substrate 302 includes an epitaxial layer. For example, the semiconductor substrate 302 may have an epitaxial layer overlying a bulk semiconductor. Furthermore, the semiconductor substrate 302 may include a semiconductor-on-insulator (SOI) structure. For example, the semiconductor substrate 302 may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable technique, such as wafer bonding and grinding.

The first semiconductor layers 304 (sometimes referred to as semiconductor sacrificial layers) and the second semiconductor layers 306 (sometimes referred to as semiconductor channel layers) are alternatingly disposed on top of one another (e.g., along the Z direction) to form a stack. For example, one of the second semiconductor layers 306 is disposed over one of the first semiconductor layers 304 then another one of the first semiconductor layers 304 is disposed over the second semiconductor layer 306, so on and so forth.

The stack may include any number of alternately disposed semiconductor layers 304 and 306. The semiconductor layers 304 and 306 may have different thicknesses. The first semiconductor layers 304 may have different thicknesses from one layer to another layer. The second semiconductor layers 306 may have different thicknesses from one layer to another layer. The thickness of each of the semiconductor layers 304 and 306 may range from few nanometers to few tens of nanometers. The first layer of the stack may be thicker than other semiconductor layers 304 and 306. In an embodiment, each of the first semiconductor layers 304 has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each of the second semiconductor layers 306 has a thickness ranging from about 5 nm to about 20 nm. Either the first semiconductor layer 304 or the second semiconductor layer 306 may be the topmost layer (or the layer most distanced from the semiconductor substrate 302). Either the first semiconductor layer 304 or the second semiconductor layer 306 may be the bottommost layer (or the layer most proximate to the semiconductor substrate 302).

The two semiconductor layers 304 and 306 have different compositions. In various embodiments, the two semiconductor layers 304 and 306 have compositions that provide for different oxidation rates and/or different etch selectivity between the layers. In an embodiment, the first semiconductor layers 304 include silicon germanium (Si_(1-x)-Ge_(x)), and the second semiconductor layers 306 include silicon (Si). In such embodiments, the first semiconductor layers 304 may sometimes be referred to as germanium (Ge) layers, and the second semiconductor layers 306 may sometimes be referred to as silicon (Si) layers. In an embodiment, each of the second semiconductor layers 306 is silicon that may be undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm⁻³ to about 1×10¹⁷ cm⁻³), where for example, no intentional doping is performed when forming the layers 306 (e.g., of silicon).

In various embodiments, the second semiconductor layers 306 may be intentionally doped. For example, when the nanostructure transistor device 300 is configured in n-type, each of the second semiconductor layers 306 may be silicon that is doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the nanostructure transistor device 300 is configured in p-type, each of the second semiconductor layers 306 may be silicon that is doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb). In another example, when the nanostructure transistor device 300 is configured in n-type, each of the second semiconductor layers 306 may be silicon that is doped with an n-type dopant instead; and when the nanostructure transistor device 300 is configured in p-type (and operates in a depletion mode), each of the semiconductor layers 306 may be silicon that is doped with a p-type dopant instead. In some embodiments, each of the first semiconductor layers 304 is Si_(1-x)Ge_(x) that includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the semiconductor layers 328 of Si_(1-x)Ge_(x) in molar ratio. Furthermore, the first semiconductor layers 304 may include different compositions among them, and the second semiconductor layers 306 may include different compositions among them.

Either of the semiconductor layers 304 and 306 may include other materials, for example, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, any other suitable material, or combinations thereof. The materials of the semiconductor layers 304 and 306 may be chosen based on providing differing oxidation rates and/or etch selectivity.

The semiconductor layers 304 and 306 can be grown from the semiconductor substrate 302. For example, each of the semiconductor layers 304 and 306 may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and/or other suitable growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate 302 extends upwardly, resulting in the semiconductor layers 304 and 306 having the same crystal orientation with the semiconductor substrate 302. The semiconductor layers 304 and 306 continuously extend along the X-direction.

Corresponding to operation 204 of FIG. 2 , FIG. 4 is a perspective view of the nanostructure transistor device 300 including a number of fin structures 400A, 400B, 400C, and 400D (which may sometimes be referred to as fin structures 400) at one of the various stages of fabrication. Each of the fin structures 400, which is elongated along the Y-direction, can include a stack of semiconductor layers 304-306 alternatively stacked with each other. Although four fin structures are shown in the illustrated embodiment of FIG. 4 (and the following figures), it should be appreciated that the nanostructure transistor device 300 can include any number of fin structures while remaining within the scope of the present disclosure.

The fin structures 400 are formed by patterning the semiconductor layers 304-306 and the semiconductor substrate 302 using, for example, photolithography and etching techniques. For example, a mask layer (sometimes referred to as a hard mask layer) is formed over the topmost semiconductor layer 306 (FIG. 3 ). In one embodiment, the mask layer can include one or more layers, each of which is formed of a semiconductor material similar to the material of semiconductor layer 304 or 306. For example, the mask layer has a single layer formed of Si_(1-x)Ge_(x) and comprises a first percentage of germanium. In some embodiments, the first percentage includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the mask layer of Si_(1-x)Ge_(x) in molar ratio. In another example, the mask layer has a stack of a first layer and a second layer, in which the first layer is formed of Si_(1-x)Ge_(x) and the second layer is formed of Si.

The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the mask layer to form a patterned mask 402 (sometimes referred to as a hard mask), as illustrated in FIG. 4 .

The patterned mask 402 is subsequently used to pattern exposed portions of the semiconductor layers 304-306 and the substrate 302 to form trenches (or openings) 410, thereby defining the fin structures 400 between adjacent trenches 410, as illustrated in FIG. 4 . The trenches 410 continuously extend along the Y-direction. When multiple fin structures are formed, such a trench may be disposed between any adjacent ones of the fin structures. In some embodiments, the fin structures 400 are formed by etching trenches in the semiconductor layers 304-306 and the substrate 302 using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, any other suitable process, or combinations thereof. The etch may be anisotropic. In some embodiments, the trenches 410 may be strips (when viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches 410 may be continuous and surround the fin structures 400.

In some embodiments, the fin structures 400 may be patterned to have the same widths along the X-direction. In other embodiments, the fin structures 400 may have different widths along the X-direction. In such embodiments, the nanostructure transistor device 300 may comprise a first region with fin structures with larger widths (e.g., 400A and 400B) and a second region with fin structures with smaller widths (e.g., 400C and 400D). Such embodiments may be expanded upon below.

Corresponding to operation 206 of FIG. 2 , FIG. 5 is a perspective view of the nanostructure transistor device 300 including isolation structures 504 (sometimes referred to as isolation regions) at one of the various stages of fabrication. As shown in FIG. 5 , each of the isolation structures 504 can be disposed between adjacent ones of the fin structures 400, and partially embed respective lower portions of the adjacent fin structures 400.

The isolation structures 504, which are formed of an insulation material, can electrically isolate neighboring active structures (e.g., fin structures 400) from each other. The isolation structures 504 continuously extend in the Y-direction. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, any other suitable material, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, any other suitable method, or combinations thereof. Other insulation materials and/or other formation processes may be used. In an example, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP) process or any other suitable process, may remove any excess insulation material and form a top surface of the insulation material and a top surface of the patterned masks 402 that are coplanar (not shown).

Next, the insulation material is recessed to form the isolation structures 504, as shown in FIG. 5 , which are sometimes referred to as shallow trench isolations (STIs). The isolation structures 504 are recessed such that the fin structures 400 protrude from between neighboring isolation structures 504. The isolation structures 504 may be recessed to where a top surface of the isolation structures 505 is below the substrate 302. Respective top surfaces of the isolation structures (STIs) 504 may have a flat surface, a convex surface, a concave surface (such as dishing) (as illustrated), any other suitable surface, or combinations thereof. The top surfaces of the isolation structures 504 may be formed flat, convex, and/or concave by an appropriate etch. The isolation structures 504 may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation structures 504. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation structures 504.

Corresponding to operation 208 of FIG. 2 , FIG. 6 is a perspective view of the nanostructure transistor device 300 including a cladding layer 600 at one of the various stages of fabrication. As shown in FIG. 6 , the cladding layer 600 can extend along a top portion and sidewalls of each of the fin structures 400.

After the isolation structures 504 are formed, the cladding layer 600 may be conformally deposited over the fin structures 400. For example, the cladding layer 600 can be formed to overlay the top surface (with the patterned mask 402, if still present, disposed therebetween) and extend along the sidewalls of each of the fin structures 400. In some embodiments, the cladding layer 600 may be epitaxially grown from the fin structures. As such, a majority of the cladding layer 600 is formed around the fin structures 400, with a minority of the cladding layer 600 formed to overlay the isolation structures 504, as shown in FIG. 6 . In some embodiments where the isolation structure is concave or convex, the minority of the cladding layer 600 formed over the isolation structures 504 may be curved as well, as shown in FIG. 6 . The cladding layer 600 may include the same material as one of the alternating first and second semiconductor layers, for example, the semiconductor layers that function as sacrificial layers. The cladding layer may have a thickness in between about 1 and about 10 nanometers, inclusive (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nanometers). As will be discussed below, the first semiconductor layers 304 may be later removed to cause the second semiconductor layers 306 to be wrapped around by an active gate structure. Thus, in the example where the first semiconductor layers 304 include silicon germanium, the cladding layer 600 may also include silicon germanium. In such embodiments, the cladding layer 600 may have a second percentage of germanium. In some embodiments, the second percentage is less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the cladding layer 600 of Si_(1-x)Ge_(x) in molar ratio.

Corresponding to operation 210 of FIG. 2 , FIG. 7 is a perspective view of the nanostructure transistor device 300 including a nitride-based dielectric layer 700 at one of the various stages of fabrication. As shown in FIG. 7 , the nitride-based dielectric layer 700 can extend along the sidewalls of the cladding layer 600 and a top portion of the isolation structures 504.

After the cladding layer 600 is formed, the nitride-based dielectric layer 700 may be conformally deposited over the sidewalls of the cladding layer 600 and the top portion of the isolation structures 504. In some embodiments, the nitride-based dielectric layer 700 may be formed on a curved concave or convex surface of the isolation structures 504, as shown in FIG. 7 . The nitride-based dielectric layer 700 may comprise SiCN or any other suitable material and may be formed by any suitable deposition process such as CVD (such as PECVD, HARP, or combinations thereof) process, ALD process, another applicable process, or a combination thereof. The nitride-based dielectric layer 700 may have a thickness in between about 1 and about 10 nanometers, inclusive (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nanometers).

Corresponding to operations 212-214 of FIG. 2 , FIG. 8 is a perspective view of the nanostructure transistor device 300 including an oxide-based layer 800 at one of the various stages of fabrication. As shown in FIG. 8 , the oxide-based layer 800 can extend along the bottom portion and the sidewalls of the nitride-based dielectric layer 700 and extends continuously in the Y-direction.

After the nitride-based dielectric layer 700 is formed, the oxide-based layer 800 is formed in the trenches 410 at operation 212. The oxide-based layer 800 may comprise a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), any other suitable material, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. The oxide-based layer 800 is first formed to be coplanar with top surfaces of the cladding layer 600. Respective top surfaces of the oxide-based layer 800 may have a flat surface (as illustrated in FIG. 8A), a convex surface, a concave surface (such as dishing), any other suitable surface, or combinations thereof. The top surfaces of the oxide-based layer 800 may be formed flat, convex, and/or concave by an appropriate etch or a planarization process, such as a CMP process. The oxide-based layer 800 may be then recessed using a suitable etching process, such as one that is selective to the material of the oxide-based layer 800, at operation 214, as shown in FIG. 8 .

Corresponding to operation 216 of FIG. 2 , FIG. 9 is a perspective view of the nanostructure transistor device 300 in which the nitride-based dielectric layer 700 is etched at one of the various stages of fabrication. As shown in FIG. 9 , the nitride-based dielectric layer 700 may be etched as having one or more tilted portions.

In some embodiments, the nitride-based dielectric layer 700 may be etched with a sulfuric peroxide mix (SPM) process or any other suitable process. In some embodiments, sulfuric acid and hydrogen peroxide are used in the etch at a temperature of about 170° C. Such a SPM process may minimize etching on the surrounding oxide-based layers 602, 702, and 800 and the cladding layer 600 while etching the nitride-based dielectric layer 700.

In some embodiments, the nitride-based dielectric layer 700 may be etched with a first tilted portion 900A and a second tilted portion 900B. The first tilted portion 900A and the second tilted portion 900B may be at an angle to a top surface of the oxide-based layer 800 less than or equal to about 30 degrees (e.g., 1, 5, 10, 15, 20, 25, or 30 degrees). The first tilted portion 900A and the second tilted portion 900B may have the same angle or different angles. In some embodiments, the height in the Z-direction between a topmost portion of the nitride-based dielectric layer 700 and a bottommost portion may be less than or equal to about 2 nanometers (e.g., 0.1, 0.5, 1, 1.5, or 2 nanometers). In other embodiments, the nitride-based dielectric layer 700 may be etched to have a flat surface.

Corresponding to operation 218 of FIG. 2 , FIG. 10 is a perspective view of the nanostructure transistor device 300 including a high-k dielectric structure 1000 formed at one of the various stages of fabrications. As shown in FIG. 10 , the high-k dielectric structure 1000 extends along the Y-direction and is disposed on a top surface of the nitride-based dielectric layer 700 and the oxide-based layer 800.

In some embodiments, the high-k dielectric structure 1000 can be deposited in the trenches 410 (FIG. 9 ) in the recess formed by the etched nitride-based dielectric layer 700 and the third oxide-based layer 800. The high-k dielectric structure 1000 extends along the Y-direction. The high-k dielectric structure 1000 may include a dielectric material such as, for example, hafnium oxide (HfO₂), zirconium oxide (ZrO₂), hafnium aluminum oxide (HfAlOx), hafnium silicon oxide (HfAlOx), aluminum oxide (Al₂O₃), or combinations thereof.

The high-k dielectric structure 1000 may fill the entirety of the trench 410 (FIG. 9 ). In some embodiments, the high-k dielectric structure 1000 may have a height in the Z-direction in between about 5 and about 20 nanometers, inclusive (e.g., 5, 10, 15, or 20 nanometers). In some embodiments, the high-k dielectric structure 1000 may have a width in the X-direction in between about 10 and about 30 nanometers, inclusive (e.g., 10, 15, 20, 25, or 30 nanometers). The width of the high-k dielectric structure 1000 in the X-direction is wider than the width of high-k dielectric structures typically observed in nanostructure transistor devices. In some embodiments, a planarization process such as a CMP process may be applied so that a top surface of the high-k dielectric structure 1000 is level with a top portion of the cladding layer 600.

Corresponding to operation 220-222 of FIG. 2 , FIGS. 11A-B are a perspective view and a cross-sectional view cut along the X-direction, respectively, of the nanostructure transistor device 300 in which the cladding layer 600 and patterned mask 402 are etched with a sequential combination of at least a first etching process and a second etching process, at one of the various stages of fabrications. As shown in FIGS. 11A-B, the cladding layer 600 may be etched to form a tilted top surface 1100.

In some embodiments, the top portion of the cladding layer 600 and the patterned mask 402 may then be removed with the first etching process and the second etching process, exposing the topmost semiconductor layer 306, with vertical portions of the cladding layer 600 and the high-k dielectric structure 1000 remaining intact. Therefore, the high-k dielectric structure 1000 may extend above the topmost semiconductor layer 306 (or 304 in other embodiments) and is disposed in between the fin structures 400A-D.

In some embodiments, the cladding layer 600 and the patterned mask 402 are etched with at least one sequential combination of the first etching process and the second etching process. The first etching process may include applying a first wet etchant over the patterned mask 402 and the cladding layer 600. In some embodiments, the patterned mask 402 may have a first percentage of Ge and the cladding layer 600 may have a second percentage of Ge. The first percentage may have higher than the second percentage so that the cladding layer 600 has more silicon. The first wet etchant may comprise may include hydrofluoric acid and liquid ozone. The first etching process may last for a first time period in a range of about 120 to about 240 seconds (120 seconds, 150 seconds, 180 seconds, 210 seconds, or 240 seconds, inclusive). In some embodiments, the first etching process may last for about 180 seconds.

The second etching process in the sequential combination may include applying a second wet etchant over the patterned mask 402 and the cladding layer 600. The second wet etchant may include ammonium and hydrogen peroxide. In some embodiments, the second wet etchant may be applied at a temperature of about 60° C. The second etching process may last for a second time period in a range of about 700 to about 2,000 seconds (e.g., 700 seconds, 720 seconds, 1000 seconds, 1250 seconds, 1440 seconds, 1500 seconds, 1750 seconds, 1920 seconds, or 2000 seconds, inclusive). In some embodiments, the second etching process may last for about 1,920 seconds.

In some embodiments, the sequential combination of the first etching process and the second etching process is repeated a number of times. In such embodiments, the first time period of the first etching process is about the same across the plurality of sequential combinations. The second time period of the second etching process may increase across the plurality of sequential combinations. In some embodiments, the second time period of the second etching process may stay about the same across the plurality of sequential combinations.

In some embodiments, the sequential combination of the first etching process and the second etching process may remove a portion or the entirety of the patterned mask 402 and a portion of the cladding layer 600. In some embodiments, more of the patterned mask 402 may be removed in comparison to the cladding layer 600 due to the higher silicon content of the cladding layer 600. In some embodiments, an entirety of the cladding layer 600 disposed over the topmost semiconductor layer (e.g., the semiconductor layer 306) may be removed. In some embodiments, the entirety of the patterned mask 402 may be removed so as to expose a top surface of the topmost semiconductor layer. In some embodiments, the topmost semiconductor layer may be a second semiconductor layer 306.

In some embodiments, the cladding layer 600 may be etched to form a plurality of tilted top surfaces 1100. Each top surface 1100 may be at an angle to the top surface of the topmost semiconductor layer less than or equal to about 60 degrees (e.g., 1 degree, 10 degrees, 20 degrees, 30 degrees, 40 degrees, 50 degrees, or 60 degrees, inclusive). Each top surface 1100 may have the same angle or different angles. In some embodiments, a vertical difference in the Z-direction between the lowest point of the top surface 1100 and the top surface of the topmost semiconductor layer (e.g., the semiconductor layer 306) may be about 0 nanometers. In some embodiments, a vertical difference in the Z-direction between a highest point of the top surface 1100 and a lowest point of the top surface 1100 may be less than or equal to about 3 nanometers (e.g., 0.1 nanometers, 0.5 nanometers, 1 nanometer, 1.5 nanometers, 2 nanometers, 2.5 nanometers, or 3 nanometers, inclusive). A smaller vertical difference between the highest point of the top surface 1100 of the cladding layer 600 and the lowest point of the top surface 1100 of the cladding layer 600 may result in a flatter profile of the nanostructure transistor device 300 which may reduce processing times, thereby increasing the efficiency of manufacturing and reducing manufacturing costs.

Corresponding to operation 224 of FIG. 2 , FIG. 12 is a perspective view of the nanostructure transistor device 300 including one or more dummy gate structures 1200 at one of the various stages of fabrication. As shown in the illustrated example of FIG. 12 , the dummy gate structures 1200, continuously extending along X-direction, can be formed over the workpiece. The dummy gate structure structures 1200 are placed where an active (e.g., metal) gate structure may later be formed, in various embodiments. Two dummy gate structures 1200 are shown in FIG. 12 , but it is understood that any number of dummy gate structures 1200 may be formed in a nanostructure transistor device.

An etching stop layer 1202 may be formed over a substantially top surface shared by the fin structures 400A-D and the high-k dielectric structure 1000. The etching stop layer 1202 may comprise a staircase formation over the high-k dielectric structure 1000 which is taller than the fin structures 400A-D. The etching stop layer 1202 may include silicon oxide or any other suitable material. The etching stop layer 1202 may be formed by a deposition process, such as CVD (such as PECVD, HARP, or combinations thereof) process, ALD process, another applicable process, or a combination thereof.

Next, the dummy gate structures 1200 are formed over the etching stop layer 1202. The dummy gate structures 1200 include a dummy gate dielectric 1204 and a dummy gate electrode 1206 in some embodiments. A mask 1205 may be formed over the dummy gate structure 1200. To form the dummy gate structure 1200, a dielectric layer is formed over the etch stop layer 1202. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or any other suitable material and may be deposited or thermally grown.

A gate layer is then formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like.

After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using suitable lithography and etching techniques to form the mask 1205. The pattern of the mask 1205 then may be transferred to the gate layer and the dielectric layer by a suitable etching technique to form the dummy gate electrode 1206 and the dummy gate dielectric 1204, respectively, to form the dummy gate structures 1200. The dummy gate structures 1200 each cover a respective central portion (e.g., a channel region) of each of the fin structures 400A-D and the high-k dielectric layers 1000.

Corresponding to operation 226 of FIG. 2 , FIG. 13 is a perspective view of the nanostructure transistor device 300 in which portions of the fin structures 400A-D and the cladding layer 600 not overlaid by the dummy structures 1200 (and the corresponding gate spacers 1300) and end portions of the semiconductor layers 304 are removed at one of the various stages of fabrication.

After the formation of the dummy gate structures 1200, the gate spacers 1300 may be formed on opposing sidewalls (and extend along the X-direction) of each of the dummy gate structures 1200. The gate spacers 1300 may be low-k spacers and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, or the like. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), or the like, may be used to form the gate spacers 1300. In some embodiments, the gate spacers 1300 may have a thickness in the Y-direction in between about 1 nanometer and about 12 nanometers, inclusive (e.g., 1, 2, 5, 7, 10, 11, and 12 nanometers) or any other suitable thickness. The shapes and formation methods of the gate spacers 1300 as illustrated and described in FIG. 13 are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

Next, the portions of the fin structures 400A-D and portions of the cladding layer 600, and (FIG. 12 ) that are not covered by the dummy gate structures 1200 and the gate spacers 1300 are removed by, for example, an anisotropic etching process using the dummy gate structures 1200 as an etching mask, although any other suitable etching process may also be used. Upon the portions of the fin structures 400A-D being removed, source/drain recesses 1304 are formed. The source/drain recesses 1304 can each expose respective “shortened” ends (along the Y direction) of each of the semiconductor layers 304 and 306.

Upon the ends of the semiconductor layers 304 and 306 being exposed (e.g., when forming the source/drain recesses 1304), respective end portions of each of the first semiconductor layers 304 and a portion of the cladding layer 600 (overlaid by the dummy gate structures 1200 and gate spacers 1300) may be concurrently removed, as the first semiconductor layers 304 and the cladding layer 600 include similar material. The end portions of the first semiconductor layers 304 and the portion of the cladding layer 600 can be removed (e.g., etched) using a “pull-back” process to pull the first semiconductor layers 304 and cladding layer 600 back by an initial pull-back distance such that the ends of the first semiconductor layers 304 terminate underneath (e.g., aligned with) the gate spacer 1300. It is understood that the pull-back distance (i.e., the extent to which each of the first semiconductor layers 304 is etched, or pulled-back) can be arbitrarily increased or decreased. In an example where the second semiconductor layers 306 include Si, and the first semiconductor layers 304 (together with the cladding layer 600) include SiGe, the pull-back process may include a hydrogen chloride (HCL) gas isotropic etch process, which etches Si_(1-x)Ge_(x) without attacking Si. As such, the second semiconductor layers 306 may remain substantially intact during this process.

Corresponding to operation 228 of FIG. 2 , FIG. 14 is a perspective view of the nanostructure transistor device 300 including inner spacers 1400 at one of the various stages of fabrication. As shown in FIG. 14 , the inner spacers 1400 can be formed along the etched ends of each of the first semiconductor layers 304 and along respective ends (along the X-direction) of each of the semiconductor layers 304 and 306.

The inner spacers 1400 can be formed conformally by chemical vapor deposition (CVD), or by monolayer doping (MLD) of nitride followed by spacer ME. The inner spacers 1400 can be deposited using, e.g., a conformal deposition process and subsequent isotropic or anisotropic etch back to remove excess spacer material on the sidewalls of the fin structures 400A-D (FIG. 12 ) and on a surface of the semiconductor substrate 302. A material of the inner spacers 1400 can be formed from the same or different material as the gate spacer 1300 (e.g., silicon nitride). For example, the inner spacers 1400 can be formed of silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant less than about 5) appropriate to the role of forming an insulating gate sidewall spacers of transistors.

Corresponding to operation 230 of FIG. 2 , FIG. 15 is a perspective view of the nanostructure transistor device 300 including epitaxial structures 1500 at one of the various stages of fabrication. As shown in the illustrated example of FIG. 15 , the epitaxial structures 1500 are formed in the source/drain recesses 1304, respectively. The epitaxial structures 1500 are coupled to respective ends (along the X-direction) of the fin structures 400A-D (FIG. 12 ), e.g., the respective “shortened” or “etched” ends of each of the second semiconductor layers 306.

The epitaxial structures 1500 may each include silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), germanium arsenide (GaAs), germanium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), any other suitable material, or combinations thereof. The epitaxial structures 1500 may be formed using an epitaxial layer growth process on exposed ends of each of the second semiconductor layers 306. For example, the growth process can include a selective epitaxial growth (SEG) process, CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epitaxial processes. In some embodiments, a bottom surface of the epitaxial structures 1500 may be leveled with the top surface of the isolation structure 504. In other embodiments, the bottom surface of the epitaxial structures 1500 may be lower than the top surface of the isolation structure 504.

In-situ doping (ISD) may be applied to form doped epitaxial structures 1500, thereby creating the junctions for the nanostructure transistor device 300. For example, when the nanostructure transistor device 300 is configured in n-type, the epitaxial structures 1500 can be doped by implanting n-type dopants, e.g., arsenic (As), phosphorous (P), etc., into them. When the nanostructure transistor device 300 is configured in p-type, the epitaxial structures 1500 can be doped by implanting p-type dopants, e.g., boron (B), etc., into them.

In some other embodiments, two adjacent ones of the epitaxial structures 1500 may merge together. With such embodiments, the dielectric layers (e.g., 700, 702, 800) between the corresponding fin structures 400, from which the merged epitaxial structures 1500 are formed, may not be formed in the previous fabrication stages. Accordingly, there may not be a high-k dielectric structure 1100 formed between these adjacent fin structures 400. For example, at the fabrication stages (e.g., corresponding to operations 210-214 of FIG. 2 ), the layers 700, 702, and 800 may not be formed between two adjacent ones of the fin structures 400 (and in turn no high-k dielectric structure 1100 formed therebetween), which can allow epitaxial structures 1500 respectively grown from these adjacent fin structures 400 to merge with each other.

Corresponding to operation 230 of FIG. 2 , FIG. 16 is a perspective view of the nanostructure transistor device 300 including an interlayer dielectric (ILD) 1600 at one of the various stages of fabrication. As shown in the illustrated example of FIG. 16 , the ILD 1600 is formed on opposing sides (along the X-direction) of each of the dummy gate structures 1200 to overlay the epitaxial structures 1500 and the oxide-based layer 800, with a contact etch stop layer 1502 disposed therebetween.

The contact etch stop layer 1602 may be first formed over the epitaxial structures 1500, the oxide-based layer 800, and the dummy gate structures 1200. The contact etch stop layer 1602 can function as an etch stop layer in a subsequent etching process, and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be formed by a suitable formation method such as CVD, PVD, combinations thereof, or the like.

The contact etch stop layer 902 may have a thickness in a range in between about 5 Angstroms and about 50 Angstroms, inclusive (e.g., 5, 15, 25, 35, 45, and 50 Angstroms) or any other suitable thickness.

Next, the ILD 1600 is formed over the contact etch stop layer 1602. The ILD 1600 extends along the X-direction. In some embodiments, the ILD 1600 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), any other suitable material, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. Next, a planarization process, such as a CMP process, may be performed to achieve a level top surface for the ILD 1600. The CMP may also remove the mask 1205 and portions of the contact etch stop layer 1602 disposed over the mask 1205. After the planarization process, the top surface of the ILD 1600 is level with a top surface of the dummy gate structures 1200, in some embodiments.

Corresponding to operation 234 of FIG. 2 , FIGS. 17A-B are a perspective view and a cross-sectional view cut along the X-direction of the nanostructure transistor device 300 in which the active gates structures 1700 (sometimes referred to as metal gate structures) are formed at one of the various stages of fabrication.

Subsequently to forming the ILD 1600 and exposing the dummy gate structures 1200 (FIG. 16 ), the dummy gate structures 1200, the etch stop layer 1202, and the first semiconductor layers 304 are sequentially removed. The dummy gate structures 1200 and the etch stop layer 1202 can be removed by an etching process, e.g., RIE, chemical oxide removal (COR), or any other suitable process. After removing the dummy gate structures 1200 and the etch stop layer 1202, the top surface of each of the fin structures 400A-D (e.g., the top surface of the topmost semiconductor layers 306) is exposed. In addition to the top surface, sidewalls of each fin structure 400 (facing the Y-direction) may be exposed. Next, the first semiconductor layers 304 are removed from each of the fin structures 400 by applying a selective etch (e.g., a hydrochloric acid (HCl)), while leaving the second semiconductor layers 306 substantially intact. After the removal of the first semiconductor layers 304, respective bottom surface and top surface of each of the second semiconductor layers 306 may be exposed.

Then, at operation 234, one or more active gate structures 1700 (sometimes referred to as gate structures) are formed in the region originally filled with the cladding layer 600. Each of the active gate structures includes a gate dielectric and a gate metal, in some embodiments. For example, in FIG. 17B, each of the active gate structures 1700 includes a gate dielectric 1702 and a gate metal 1704.

As shown in FIG. 17A, the active gate structures 1700 may be disposed in the exposed cavities left by the dummy gate structures 1200 the first semiconductor layers 304, and the cladding layer 600. In some embodiments, the active gate structures 1700 disposed above the second semiconductor layer 306 may have a height in the Z-direction in a range in between about 5 nanometers to 30 nanometers, inclusive (e.g., 5, 7, 10, 15, 20, 25, and 30 nanometers). In some embodiments, the active gate structures 1700 disposed above the second semiconductor layers 306 may have a width in the Y-direction in a range in between about 9 and about 100 nanometers, inclusive (e.g., 9, 10, 15, 20, 30, 40, 50, 60, 70, 80, 90, and 100 nanometers).

In some embodiments, a subset of the second semiconductor layers 306 that are vertically arranged from one another is collectively configured as the channel structure of a nanostructure FET device. In some embodiments, multiple such subsets can collectively be configured as the channel structure of a nanostructure FET device. The plurality of second semiconductor layers 306 comprises nanostructures (e.g., nanosheets, nanowires, etc.) and results in a plurality of nanostructures vertically spaced apart from one another. At least one end of each of the nanostructures is coupled to the epitaxial structures 1500. In such embodiments, the gate structures 1700 formed from the gate dielectric and the gate metal wrap around each of the plurality of nanostructures. In some embodiments, the high-k dielectric structure 1000 may be disposed between separate channel structures, as shown in FIG. 17B.

As shown in FIG. 17B, the gate dielectric 1702 wraps around each of the second semiconductor layers 306, e.g., the top and bottom surfaces and sidewalls perpendicular to the Y direction). The gate dielectric 1702 may be formed of different high-k dielectric materials or a similar high-k dielectric material. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric 1702 may include a stack of multiple high-k dielectric materials. The gate dielectric 1702 can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the gate dielectric 1702 may optionally include a substantially thin oxide (e.g., SiO_(x)) layer.

The gate metal 1704 can wrap around each of the second semiconductor layers 306 with the gate dielectric 1702 disposed therebetween. Therefore, the active gate structures 1700 straddle the channel structures. Specifically, the gate metal 1704 can include a number of gate metal sections abutted to each other along the Z direction. Each of the gate metal sections can extend not only along a horizontal plane (e.g., the plane expanded by the X direction and the Y direction), but also along a vertical direction (e.g., the Z direction). As such, two adjacent ones of the gate metal sections can adjoin together to wrap around a corresponding one of the second semiconductor layers 306, with the gate dielectric 1702 disposed therebetween.

The gate metal 1704 may include a stack of multiple metal materials. For example, the gate metal 1704 may be a p-type work function layer, an n-type work function layer, multi-layers thereof, any other suitable material, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals that may include TiN, TaN, Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage V_(t) is achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.

As shown in FIG. 17B, the high-k dielectric structures 1000 are disposed in between and isolate the gate structures 1700 along the X-direction. The high-k dielectric structures 1000 comprise a first portion extending into the gate structures along the X-direction. Each high-k dielectric structure 1000 has a lengthwise direction extending along the Y-direction across the epitaxial structures 1500 and the second semiconductor layers 306 containing nanostructures. The high-k dielectric structures 1000 comprise a second portion (sometimes referred to as the bottom surface) vertically lower than the first portion.

Corresponding to operation 236 of FIG. 2 , FIGS. 18A-B are a perspective view and a cross-sectional view along the X-direction of the nanostructure transistor device 300 including dielectric structures 1802, 1804, and 1806 at one of the various stages of fabrication. For clarity of illustration, FIG. 18B is a corresponding cross-sectional view of the nanostructure transistor device 300 that is cut along cross-section A-A (e.g., along a longitudinal direction of one of the active gate structures 1700) indicated in FIG. 18A.

Upon forming the active gate structures 1700, an upper portion of the gate metal 1704 may be removed. In some embodiments, the upper portion of the gate metal 1704 is removed by a planarizing process, e.g., a CMP process, until the patterned portions of the high-k dielectric structure 1000 (as illustrated in FIG. 18B) are again exposed. Next, the remaining portion of the gate metal 1704 is etched back by an etching process, therefore causing the patterned portions of the high-k dielectric structure 1000 to protrude above a top surface of the gate metal 1704. The patterned portions of the high-k dielectric structure 1000 can cut the gate metal 1704, which causes a number of gate metal segments 1704A, 1704B, 1704C, and 1704D to be formed.

Next, a conductive layer 1800 is selectively formed over the gate metal 1704, and a dielectric layer 1801 is formed over the conductive layer 1800. The conductive layer 1800 is configured to reduce the resistance of the gate metal 1704. In some embodiments, the conductive layer 1800 may include tungsten (W). The conductive layer 1800 may be selectively formed over the gate metal 1704, but not formed over the patterned portions of the high-k dielectric structure 1000. In some embodiments, the dielectric layer 1801 may include silicon nitride, silicon oxynitride (SiON), silicon carbide (SiC), another applicable insulating material, or combinations thereof.

In some embodiments, prior to the formation of the conductive layer 1800, a surface treatment process may be performed on the top surface of the gate metal 1704 (e.g., the gate metal segments 1704A-D) to generate some hydrogen radicals, and then a deposition process with a precursor is performed on the treated top surface of the gate metal 1704 to selectively form the conductive layer 1800 on the gate metal segments 1704A-D. The surface treatment process can include using hydrogen (H₂) gas to generate hydrogen radicals. The precursor, which can include tungsten (W)-containing material such as, for example, tungsten hexafluoride (WF₆) or tungsten hexachloride (WCl₆), can react with the hydrogen radicals to selectively form the conductive layer 1800.

Next, the dielectric structures 1802, 1804, and 1806 can be formed in the dielectric layer 1801. In some embodiments, the dielectric structures 1802, 1804, and 1806 may include silicon nitride, silicon oxynitride (SiON), silicon carbide (SiC), another applicable insulating material, or combinations thereof. After the dielectric layer 1801 is deposited, it may be patterned to form trenches extending therethrough and exposing the patterned portions of the high-k dielectric structure 1000. The dielectric structures 1802, 1804, and 1806 are then formed by filling the trenches with at least one of the forgoing insulating materials. The dielectric structures 1802, 1804, and 1806 can be used to further electrically isolate the gate metal segments 1704A-D. For example, the dielectric structure 1802 can electrically isolate the gate metal segments 1704A and 1704B; the dielectric structure 1804 can electrically isolate the gate metal segments 1704B and 1704C; and the dielectric structure 1806 can electrically isolate the gate metal segments 1704C and 1704D. In some other embodiments, the conductive layer 1800 may globally be formed over the workpiece, e.g., overlaying both the gate metal 1704 and the patterned portions of the high-k dielectric structure 1000. As such, after depositing the dielectric layer 1801 over the conductive layer 1800, the above-mentioned trenches may be formed to extend through both of the dielectric layer 1801 and the conductive layer 1800, thereby causing the dielectric structures to electrically isolate the gate metal segments 1704A-D.

In accordance with various embodiments, the gate metal segments 1704A-D may function as respective gates of a number of transistors. As a non-limiting example, the gate metal segment 1704A may function as the gate of a first nanostructure transistor that has the second semiconductor layers 306 of the fin structures 400A as its conduction channel; the gate metal segment 1704B may function as the gate of a second nanostructure transistor that has the second semiconductor layers 306 of the fin structures 400B as its conduction channel; the gate metal segment 1704C may function as the gate of a third nanostructure transistor that has the second semiconductor layers 306 of the fin structures 400C as its conduction channel; and gate metal segment 1704D may function as the gate of a fourth nanostructure transistor that has the second semiconductor layers 306 of the fin structures 400D as its conduction channel. Further, the epitaxial structures 1500 formed on respective ends of each of the conduction channels may function as respective source and drain of the corresponding nanostructure transistor.

In some other embodiments, two or more adjacent gate metal segments may merge together as one single gate metal (segment) to wrap around two or more fin structures. In such a case, these two or more merged gate metal segments can function as the gate of a nanostructure transistor that has those two or more fin structures as its conduction channel (which is sometimes referred to as a multi-channel transistor). To fabricate such a multi-channel transistor while keeping some other transistors having a single channel, at least a majority portion of the high-k dielectric structure 1100 between those adjacent fin structures 400 may be selectively removed prior to depositing the gate dielectric 1702 and gate metal 1704. Alternatively stated, at least a majority portion of the high-k dielectric structure 1100 between two adjacent fin structures 400 is replaced with the gate metal 1704. As such, while polishing the upper portion of the gate metal 1704, in addition to the gate metal segments that respectively wrap around the fin structures 400, a portion of the gate metal 1704 can remain as connecting two or more of the gate metal segments, which allows two of more gate metal segments to merge with each other and form the gate of a multi-channel transistor.

Although the above-described operations of the method 100 are directed to forming the nanostructure transistor device 300 in either an n-type or p-type, it should be appreciated that the method 200 is not limiting thereto. In other words, the method 200 can be used to form a nanostructure transistor device having both n-type and p-type nanostructure transistors.

For example, the first region of a semiconductor substrate may be defined to form a number of n-type nanostructure transistors, and the second region of the semiconductor substrate may be defined to form a number of p-type nanostructure transistors by forming fin structures (e.g., 400) having different conduction types in the respective first and second regions. Prior to forming the fin structures, a p-type well can be formed in the first region; and an n-type well can be formed in the second region. Next, a first fin structure including alternating first and second semiconductor layers in p-type can be formed from the p-type well; and a second fin structure including alternating first and second semiconductor layers in n-type can be formed from the n-type well. In some embodiments, a fin structure formed from the p-type well will have a width less than a fin structure formed from n-type well. For example, the fin structures 400A and 400B, as shown in FIG. 18A-B, may be formed from n-type wells. The fin structures 400C and 400D may be formed from p-type wells. The fin structures 400C and 400D may have a width in the X-direction that is less than a width of the fin structures 400A and 400B. By performing the rest of operations of the method 200 with certain operations respectively performed in the first and second regions, the n-type nanostructure transistors and p-type nanostructure transistors can be formed in the first and second regions, respectively. For example, when forming the epitaxial structures for the n-type and p-type nanostructure transistors (e.g., operation 228 of FIG. 2 ), the corresponding operations may be performed in the first and second regions, respectively.

In one aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.

In another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a first fin structure and a second fin structure parallel with each other. Each of the first fin structure and the second fin structure comprises a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of each of the first and second fin structures. The method further includes patterning the semiconductor cladding layer be performing a plurality of sequential combinations of a first etching process and a second etching process. A first time period for which the first etching process is performed across the plurality of combinations is about the same. A second time period for which the second etching process is performed across the plurality of combinations is increased.

In yet another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a stack structure including a plurality of silicon (Si) layers and a plurality of germanium (Ge) layers alternatively disposed on top of one another. A topmost layer of the stack structure is one of the Si layers. The method further includes forming a hard mask over the stack structure. The hard mask contains silicon germanium (Si_(1-x)Ge_(x)) with a first percentage of Ge. The method further includes patterning the stack structure based on the hard mask to form a fin structure. The method further includes forming a cladding layer extending along sidewalls of the fin structure. The cladding layer contains Si_(1-x)Ge_(x) with a second percentage of Ge higher than the first percentage. The method further includes removing the hard mask and patterning the cladding layer by performing at least one sequential combination of a first etching process and a second etching process which causes a vertical difference between a top surface of the topmost layer and a lowest point of a top surface of the cladding layer to be substantially zero.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method for fabricating a semiconductor device, comprising: forming a fin structure that comprises a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers; forming a semiconductor cladding layer extending along sidewalls of the fin structure; and patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process, wherein a vertical difference between the highest point and the lowest point is less than 3 nanometers.
 2. The method of claim 1, further comprising forming a hard mask over the fin structure, wherein a topmost one of the plurality of semiconductor channel layers contains silicon (Si), the hard mask contains silicon germanium (SiGe) with a first percentage of Ge, and the semiconductor cladding layer contains SiGe with a second percentage of Ge, the first percentage being higher than the second percentage.
 3. The method of claim 2, wherein the first etching process comprises applying a first wet etchant over the hard mask and the semiconductor cladding layer, the first wet etchant including hydrofluoric acid and liquid ozone.
 4. The method of claim 2, wherein the second etching process comprises applying a second wet etchant over the hard mask and the semiconductor cladding layer, the second wet etchant including ammonium and hydrogen peroxide.
 5. The method of claim 1, wherein the first etching process lasts for about 180 seconds, and the second etching process lasts for at least about 1,920 seconds.
 6. The method of claim 1, wherein the second etching process is performed at an elevated temperature of about 60 degrees Celsius.
 7. The method of claim 1, further comprising: forming a nitride-based layer extending along a sidewall of the semiconductor cladding layer; forming an oxide-based layer extending along a sidewall of the nitride-based layer; and forming a high-k dielectric structure on a portion of the nitride-based dielectric layer and a portion of the oxide-based layer.
 8. The method of claim 1, further comprising replacing the plurality of semiconductor sacrificial layers of the fin structure and a portion of the semiconductor cladding layer to form a gate structure wrapping around each of the semiconductor channel layers.
 9. The method of claim 8, wherein the plurality of semiconductor channel layers comprises a plurality of nanostructures vertically spaced apart from one another.
 10. A method for fabricating a semiconductor device, comprising: forming a first fin structure and a second fin structure parallel with each other, wherein each of the first fin structure and second fin structure comprises a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers; forming a semiconductor cladding layer extending along sidewalls of each of the first and second fin structures; and patterning the semiconductor cladding layer by performing a plurality of sequential combinations of a first etching process and a second etching process, wherein a first time period for which the first etching process is performed across the plurality of combinations is about the same, and a second time period for which the second etching process is performed across the plurality of combinations is increased.
 11. The method of claim 10 wherein patterning the semiconductor cladding layer comprises forming a top surface with a highest point and a lowest point, wherein a vertical difference between the highest point and the lowest point is less than 3 nanometers.
 12. The method of claim 10, further comprising a hard mask over the first fin structure and the second fin structure, wherein a topmost one of the plurality of semiconductor channel layers contains silicon (Si), the hard mask contains silicon germanium (SiGe) with a first percentage of Ge, and the semiconductor cladding layer contains SiGe with a second percentage of Ge, the first percentage being higher than the second percentage.
 13. The method of claim 12, wherein the first etching process comprises applying a first wet etchant over the hard mask and the semiconductor cladding layer, the first wet etchant including hydrofluoric acid and liquid ozone.
 14. The method of claim 12, wherein the second etching process comprises applying a second wet etchant over the hard mask and the semiconductor cladding layer, the second wet etchant including ammonium and hydrogen peroxide.
 15. The method of claim 10, further comprising: lining a trench between the first fin structure and the second fin structure with a dielectric layer; filling the trench with an oxide-based layer; and forming a high-k dielectric structure in contact with a portion of the dielectric layer and a portion of the oxide-based layer replacing the plurality of semiconductor sacrificial layers of the first fin structure and a portion of the semiconductor cladding layer to form a first gate structure wrapping around each of the semiconductor channel layers of the first fin structure; and replacing the plurality of semiconductor sacrificial layers of the second fin structure and a second portion of the semiconductor cladding layer to form a second gate structure wrapping around each of the semiconductor channel layers of the second fin structure; wherein the first gate structure and the second gate structure are isolated from each other with at least the high-k dielectric structure.
 16. The method of claim 15, wherein the dielectric layer comprises a curved top surface, the oxide-based layer comprises a curved bottom surface, and the semiconductor cladding layer comprises a curved bottom surface.
 17. A method for fabricating a semiconductor device, comprising: forming a stack structure including a plurality of silicon (Si) layers and a plurality of germanium (Ge) layers alternatively disposed on top of one another, wherein a topmost layer of the stack structure is one of the Si layers; forming a hard mask over the stack structure, the hard mask containing silicon germanium (SiGe) with a first percentage of Ge; patterning the stack structure based on the hard mask to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure, the cladding layer containing SiGe with a second percentage of Ge higher than the first percentage; and removing the hard mask and patterning the cladding layer by performing at least one sequential combination of a first etching process and a second etching process, thereby causing a vertical difference between a top surface of the topmost layer and a lowest point of a top surface of the cladding layer to be substantially zero.
 18. The method of claim 17, wherein the vertical difference between a highest point of the top surface of the cladding layer and the lowest point of the top surface of the cladding layer is less than 3 nanometers.
 19. The method of claim 17, wherein the first etching process comprises applying a first wet etchant over the hard mask and the semiconductor cladding layer, the first wet etchant including hydrofluoric acid and liquid ozone
 19. The method of claim 16, wherein the second etching process comprises applying a second wet etchant over the hard mask and the semiconductor cladding layer, the second wet etchant including ammonium and hydrogen peroxide.
 20. The method of claim 17, further comprising replacing a portion of the plurality of germanium (Ge) layers of the fin structure to form a gate structure wrapping around each of the plurality of silicon (Si) layers of the fin structure. 